1. Field of the Invention
This invention relates to a coding apparatus and method, a decoding apparatus and method, and a recording medium, and more particularly relates to a coding apparatus and method, a decoding apparatus and method, and a recording medium that are capable of performing coding processing and decoding processing with a simple structure.
2. Description of the Related Art
FIG. 1 shows an exemplary structure of a conventional recording/reproduction apparatus 1. In the recording/reproduction apparatus 1, trellis coding processing of the coding rate of 16/20 is performed, which is being practically used in AIT2 (Advanced Intelligent Tape System 2) tape streamer system (tape streamer drive system; product of Sony Corp.) disclosed in Japanese Patent Application No. Hei 10-207372.
For example, the video data and/or audio data to be recorded in a medium 2 are supplied to a coder 11 in units of m (=16) bits. The coder 11 converts (codes) the input data word of 16 bits to the coded word having a code length of n (=20) bits, and supplied it to a D/A converter 12. The D/A converter 12 subjects the coded word supplied from the coder 11 to NRZ (non-return to zero) modulation (modulation in which the coded word corresponds to recording (transfer) waveform as it is) to convert it to the recording short waveform, and supplies it to a recording/reproducing apparatus 13.
The recording/reproducing apparatus 13 comprising a magnetic head records the recording short waveform supplied from the D/A converter 12 on the medium 2 (magnetic tape). The recording/reproducing apparatus 13 reproduces the signal recorded on the medium 2, and supplies the reproduced signal (reproduced wave) to an analog equalizer 14.
The analog equalizer 14 equalizes the reproduced wave supplied from the recording/reproducing apparatus 13 to the predetermined target equalization characteristic and then supplied the equalized wave to an A/D converter 15. The A/D converter 15 converts the equalized wave supplied from the analog equalizer 14 to the digital signal, and supplies it to the code detector 16. In the case that the equalization by means of the analog equalizer 14 is supposed to be not sufficient, a digital equalizer may be provided between the A/D converter 15 and the code detector 16.
The code detector 16 comprising a maximum likelihood detector calculates the likelihood degree based on the equalization signal supplied from the A/D converter 15, detects the code word of 20 bits based on the calculation result (maximum likelihood), and supplies the code word to a decoder 17.
The decoder 17 decodes the code word of 20 bits supplied from the code detector 16 to the data word of 16 bits, and supplies it to an external error corrector.
In the case of this example, an error corrector (ECC (error correction code)) for correcting the output data is omitted.
FIG. 2 shows an exemplary structure of the coder 11. A coding circuit 21 converts the input data word of 16 bits to the code word having a code length of 20 bits, and supplies it to a state detection circuit 22 and a code word conversion circuit 25. In the case of this example, the code word converted by the coding circuit 21 takes the sequence of RDS (running digital sum) and ADS (alternating digital sum) that satisfy seven restrictions, namely the first to seventh restrictions described below:
The first restriction: “ADS ranges from 0 to 10 or the RDS amplitude (DSV (digital sum variation)) is 10, and ADS ranges from 0 to 10 or the ADS amplitude (ADSV (alternating digital sum variation)) is 10.”
The second restriction: “The start point state and the end point state should be state (3, 3), state (3, 7), state (7, 3), and state (7, 7) in the finite state transition diagram shown in FIG. 3.” Each state is represented as state (ADS, RDS) in the finite state transition diagram shown in FIG. 3.
The third restriction: “(1) A path started from the state having ADS of 3 at the time 0 should not pass the state having ADS of 0 and the state having ADS of 2 at the time 7. (2) A path started from the state having ADS of 7 at the time 0 should not pass the state having ADS of 8 and the state having ADS of 10 at the time 7.”
The fourth restriction: “(1) A path started from the state having RDS of 3 at the time 0 should satisfy the following four restriction, the path:                (a) should not pass the state having RDS of 0 at the time 3,        (b) should not pass the state having RDS of 10 at the time 7,        (c) should not transit to the state having RDS of 10 at the time 15 from the state having RDS of 0 at the time 5 with increment of RDS one by one, and        (d) should not transit to the state having RDS of 10 at the time 17 from the state having RDS of 0 at the time 7 with increment of RDS one by one.        
(2) A path started from the state having RDS of 7 at the time 0 should satisfy the following four restrictions, the path;                (a) should not pass the state having RDS of 10 at the time 3,        (b) should not pass the state having RDS of 0 at the time 7,        (c) should not transit to the state having RDS of 0 at the time 15 from the state having RDS of 10 at the time 5 with increment of RDS one by one, and        (d) should not transit to the state having RDS of 10 at the time 7 from the state having RDS of 0 at the time 17 with increment of RDS one by one.”        
The fifth restriction: “(1) In the case that the start point of the code coded by means of the coding circuit 21 is the state (3, 3), the path having ADS of 3 at the time 6, ADS of 4 at the time 4, and ADS of 3 at the time 8 out of the paths started from this state at the time 0 should not have RDS of 7 at any time.
(2) In the case that the start point of the code coded by means of the coding circuit 21 is the state (3, 7), the path having ADS of 3 at the time 6, ADS of 4 at the time 8, and ADS of 3 at the time 8 out of the paths started from this state at the time 0 should not have RDS of 3 at any time.
(3) In the case that the start point of the code coded by means of the coding circuit 21 is the state (7, 3), the path having ADS of 7 at the time 6, ADS of 6 at the time 7, and ADS of 7 at the time 8 out of the paths started from this state at the time 0 should not have RDS of 7 at any time,
(4) In the case that the start point of the code coded by means of the coding circuit 21 is the state (7, 7), the path having ADS of 7 at the time 6, ADS of 6 at the time 7, and ADS of 7 at the time 8 out of the paths started from this state at the time 0 should not have RDS of 3 at any time.”
The sixth restriction: “(1) In the case that RDS of the start point of the code coded by means of the coding circuit 21 is 3, the path having RDS of 6 at the time 3 out of the paths started from this state at the time 0 should have RDS of 7 at some time.
(2) In the case that RDS of the start point of the code coded by means of the coding circuit 21 is 7, the path having RDS of 4 at the time 3 out of the paths started from this state at the time 0 should have RDS of 3 at some time.
The seventh restriction: “(1) In the case that RDS of the start point of the code coded by means of the coding circuit 21 is 3, the path started from this state at the time 0 should satisfy the following four restrictions, the path;                (a) should not have RDS of 1 at the time 2, RDS of 2 at the time 3, RDS of 1 at the time 4, and RDS of 7 or larger at any time,        (b) should not have RDS of 1 at the time 4, RDS of 2 at the time 5, RDS of 1 at the time 6, and RDS of 9 at the time 14, and RDS of 8 at the time 15, and RDS of 9 at the time 16,        (c) should not have RDS of 1 at the time 6, RDS of 2 at the time 7, RDS of 1 at the time 8, and RDS of 9 at the time 16, and RDS of 8 at the time 17, and RDS of 9 at the time 18, and        (d) should not have RDS of 9 at the time 6, RDS of 8 at the time 7, and RDS of 9 at the time 8.        (2) In the case that RDS of the start point of the code coded by means of the coding circuit 21 is 7, the path started from this state at the time 0 should satisfy the following four restrictions, the path;        (a) should not have RDS of 9 at the time 2, RDS of 8 at the time 3, RDS of 9 at the time 4, and RDS of 3 or smaller at any time,        (b) should not have RDS of 9 at the time 4, RDS of 8 at the time 5, RDS of 9 at the time 6, and RDS of 1 at the time 14, and RDS of 2 at the time 15, and RDS of 1 at the time 16,        (c) should not have RDS of 9 at the time 6, RDS of 8 at the time 7, RDS of 9 at the time 8, RDS of 1 at the time 16, RDS of 2 at the time 17, and RDS of 1 at the time 18, and        (d) should not have RDS of 1 at the time 6, RDS of 2 at the time 7, and RDS of 1 at the time 8.”        
As described above, RDS and ADS are restricted.
Next, the first restriction, the third restriction, and the fourth restriction will be described out of the above-mentioned seven restrictions.
At first, the first restriction will be described. Recently, as one effective method for reducing the code error rate of digital transmission signal, the trellis coding modulation has been studied and developed. The trellis coding modulation is a method for calculating the maximum likelihood by applying the coding rule used in the coder 11 shown in FIG. 1 to the maximum likelihood calculation in the code detector 16. The minimum Euclidean distance is increased and the code error rate is decreased by detecting the maximum likelihood by means of this method.
As one of codes used for trellis coding modulation, MSN (matched spectral null) code in which the amplitude (DSV) of RDS and/or the amplitude (ADSV) of ADS is restricted to a finite value and the null point of the code spectrum on the frequency axis is identical with the null point of the equalization signal spectrum has been known.
MSN code for the dicode equalization channel having (1−D) (D denotes the delay operator for representing 1 bit delay on the frequency axis) equalization characteristic is provided by applying a method in which ADSV is controlled below a certain value, namely DSV is rendered finite, and the DC component of the code spectrum is rendered null (by removing DC component).
Furthermore, MSN code for the duobinary channel, namely PR1 (partial response class-I) equalization channel having (1+D) equalization characteristic or PR2 (partial response class-II) equalization channel having (1+D)2 equalization characteristic is provided by applying a method in which ADSV is controlled below a certain value, namely ADSV is rendered finite, and the Nyquist frequency component is rendered null (by removing Nyquist frequency component).
MSN code for PR4 (partial response class-IV) equalization channel having (1−D)(1+D) equalization characteristic is provided by applying a method in which the code is subjected to interleave every 1 bit and the DC component of the code spectrum and Nyquist frequency components of the code are both rendered null. Kretzmer proposes the partial response classification such as PR1, PR2, or PR4, and the detail is presented in the literature: [3] E. R. Kretzmer, “Generalization of a Technique for Binary Data Communication” IEEE Trans. on com. Tech., pp.67-78, February 1966.
The equalization channel such as PR1 equalization or PR2 equalization having the equalization characteristic represented by polynominal expression of (1+D)x (x is a natural number) is more effective in high frequency band suppression than the equalization channel such as PR4 equalization or EPR4 (extended PR4) equalization having the equalization characteristic represented by polynominal expression of (1−D) (1+D)x, as the result the higher line recording density is obtained in the case that the track width is the same.
PR1 equalization and PR2 equalization are described further below. As described above, in PR1 equalization and PR2 equalization, though Nyquist frequency of the code spectrum is removed, it is required to remove the DC component of the code spectrum when PR1 equalization or PR2 equalization is used because DC component of the equalization signal spectrum is included in PR1 equalization and PR2 equalization.
When the equalization channel (PR1 equalization and PR2 equalization) that include DC component of the equalization signal spectrum and the recording signal from which DC component of the code spectrum is not removed are used combinedly, for example, in the case that the recording/reproduction apparatus 1 is a magnetic recording/reproducing apparatus (in the case that the medium 2 is, for example, a magnetic disc or a magnetic tape), because the equalization signal spectrum requires DC component though DC component has not been transmitted, the noise amplification near DC component is very large in the analog equalization processing by means of the analog equalizer 14, and as the result SN ratio becomes very poor. In the case that the recording/reproducing apparatus 1 is an optical recording/reproducing apparatus (in the case that the medium 2 is, for example, an optical disc or a magneto-optic disc), because DC component of the code spectrum is not removed from the recording code though DC component has been transmitted, the low frequency component of the reproduced signal fluctuates and the reference level fluctuates, and as the result the phase sync circuit PLL (Phase Locked Loop) could operate erroneously or the servo signal could be supplied not surely.
On the reason described above, it is necessary to intercept (remove) DC component (DC component of the recording code) of the code spectrum when PR1 equalization or PR2 equalization is applied. In other words, it is necessary to use a code from which DC component and Nyquist frequency component have been removed (referred to as DC/Nyquist free code hereinafter).
Two methods used to null (remove) both DC component and Nyquist frequency component of the code spectrum are available. The one is (1) a code word is generated based on the finite state transition diagram having finite DSV and the generated code word is subjected to interleave every 1 bit, and the other is (2) a code word is generated based on the finite state transition diagram having finite DSV and finite ADSV. In the case of the method (1), DSV after interleave is double the DSV before interleave and ADSV after interleave is double the ADSV before interleave. Therefore, for example, in the case of PR1 equalization that is the method in which the code is observed continuously to detect the code, the number of states during code detection is double in comparison with the case of PR4 that is the method in which the code is observed every 1 bit to detect the code.
On the other hand, in the case of the method (2), the value of DSV and ADSV obtained by observing the code continuously is restricted to the small value easily. Therefore, in the case of this example, the code is generated based on the finite state transition diagram shown in FIG. 3 in which the method (2) is employed, RDS is restricted in a range from 0 to 10 and DSV is restricted to 10 (finite), and ADS is restricted in a range from 0 to 10 and ADSV is restricted to 10 (finite) by means of the first restriction. In other words, by means of the first restriction, DC component and Nyquist frequency component of the code spectrum are removed from the code word.
There are 57 states in the finite state transition diagram shown in FIG. 3, “0” or “1” generated from the state indicates the NRZ code output by NRZ modulation of the code word in the D/A converter 12. In other words, the finite state transition diagram is structured on the premise of NRZ modulation.
In the finite state transition diagram, RDS and ADS in each state are assigned so that the difference between RDS and ADS is an even number (including 0) (both RDS and ADS are an even or odd number). Though the finite state transition diagram can be structured so that the difference between RDS and ADS is an odd number, in this case, because the number of code words to be generated is usually less than that to be generated in the coding processing based on the finite state transition diagram shown in FIG. 3 in many cases, the coding processing based on the odd number finite state transition diagram is not used.
The Shannon capacity in the finite state transition diagram shown in FIG. 3 is 0.8962. The Shannon capacity is the theoretical maximum value of the code conversion efficiency that is achievable for the code that satisfies the restriction condition of a certain finite state transition diagram.
The structuring method for structuring a finite state transition diagram on the premise that DSV and ADSV are both finite and NRZ modulation is applied as in the case of the finite state transition diagram shown in FIG. 3 is disclosed in, for example, the literature [4] L. J. Fredrickson, “On the Shannon Capacity of DC- and Nyquist-Free Codes,” IEEE Trans. on Info. Theory, Vol. 37, No. 3, May 1991.
Next, the third restriction will be described. To use MSN code, it is necessary to remove all the sequences having the estimation signal that cannot be likely finalized when the maximum likelihood is detected in the code detector 16, namely quasi-catastrophic sequence (referred to as QCS hereinafter) from the sequences. The time-varying trellis method is available as one effective method for removing QCS in MSN code, and the time-varying trellis method includes some methods such as trellis removing method (pruned trellis), state rearrangement method (state permutation), and set partitioning method or the like. In this example, the set partitioning method is employed.
According to the set partitioning method, ADS of the code word that starts from the state with ADS of 3 out of codes that start from any one of the state (3, 3), state (3, 7), state (7, 3), and state (7, 7) shown in the second restriction should not be 3 or smaller at any one time, and the ADS of the code word that starts from the state with ADS of 7 should not be equal to 7 or larger at any one same time, and in the case of this example, the time that is subjected to restriction is assigned to the time 7. In other words, by applying the third restriction, QCS is removed by means of the set portioning method. The detailed description of various time-varying trellis methods are disclosed in the literature [1] L. Fredrickson, et al., “Improved trellis-coding for partial-response channels,” IEEE Trans. on Magn., Vol. 31, No. 2, pp. 1141-1148, March 1995. The inventor of the present invention has also developed a QCS deletion method according to a new trellis removing method already, and the detail is disclosed in the literature [2] M. Noda, “High-Rate Matched Spectral Null Code”, IEEE Trans. on Magn., Vol. 34, No. 4, pp. 1946-1948, 1998 (or Japanese Patent Application No. Hei 09-347649)
In the trellis diagram (described hereinafter), the maximum bit length (referred to as TD (truncation depth) hereinafter) for summing the minimum Euclidean distance indicates the minimum length of path memory that is required for the code detector 16. Because TD in the trellis diagram corresponding to the code from which all the QCS are removed is finite, the code detector 16 has the path memory for it, on the other hand in the case that all the QCS are not removed, because TD in the trellis diagram is infinite, the infinite path memory is required for the code detector 16. Actually such code detector 16 is unrealistic, it is necessary that all the QCS are removed without exception.
Even in the case that TD is finite, it is required for the code detector 16 to have the path memory sufficient for it. Therefore, TD is desirably as short as possible to simplify the structure of the code detector 16.
For example, in the case that a code detector having a finite path memory is used for the code from which QCS has not been removed or in the case that a code detector having a path memory shorter than TD is used for the code from which QCS has been removed, the error rate after code detection is poor.
Next, the fourth restriction will be described. The same bit occurs sequentially most continuously in the case that RDS increases one by one from the minimum RDS to the maximum RDS and in the case that RDS decreases one by one from the maximum RDS to the minimum RDS in the finite state transition diagram shown in FIG. 3. In detail, the length of the maximum sequential same bit (referred to as the maximum sequential length Tmax hereinafter) is 10T (T=clock time interval).
If the maximum sequential length Tmax is large, for example, the over write erasion rate in magnetic recording/reproduction is reduced, over write noise increases, SN ratio of equalization signal becomes poor, cross talk from adjacent track becomes large in azimuth recording, and the data is reproduced not correctly. The information for synchronization (phase error information) decreases in PLL, and erroneous operation occurs. On the above-mentioned reason, the maximum sequential length is desirably as short as possible.
By inhibiting the transition from the state having RDS of 0 to the state having RDS of 10 through 10 times state transition and by inhibiting the transition from the state having RDS of 10 to the state having RDS of 0 through 10 times state transition in the finite state transition diagram shown in FIG. 3, all the code words that likely have the maximum sequential length Tmax of 10T are removed, and the maximum sequential length Tmax will be 9T. In other words, by applying the fourth restriction, all the code words having the maximum sequential length Tmax of 10T are removed, and the maximum sequential length will be 9T.
The description returns to FIG. 2. The state detection circuit 22 detects the state of the end point of the code word supplied from the coding circuit 21, and supplies it to the end point state correction circuit 23 as a temporary state of the end point of the cord word that is to be coded this time. The state detection circuit 22 detects the type of the input code word, and supplies the code word type parity that indicates the type of the detected code word to a code word conversion circuit 25.
The end point correction circuit 23 operates the end point state of the code word that is to be generated this time from the code word conversion circuit 25 based on the state supplied from the state detection circuit 22 (temporary state of the end point) and the start point of the code word to be generated this time from the code word conversion circuit 25 stored in a register 24 (the state of the end point of the code word generated previously from the code word conversion circuit 25), and supplies it to the register 24.
The code word conversion circuit 25 receives the code word supplied from the coding circuit 21, the code word type parity supplied from the state detection circuit 22, and the state supplied from the register 24. The code word conversion circuit 25 converts the cord word supplied from the coding circuit 21 to the code word having the starting point of the state supplied from the register 24 based on the type of the code word indicated by means of the code word type parity supplied from the state detection circuit 22.
Next, the outline of the coding processing in the coder 21 will be described. In the finite state transition diagram shown in FIG. 3, there are 124416 code words that satisfy the second restriction. Out of these cord words, 82944 cord words have the start point state of the state (7, 3) and satisfy the third restriction (in this case (2)), 82944 cord words have the start point state of the state (3, 7) and satisfy the third restriction (in this case (1)), and these code words are in the total inversion code relation each other. In other words, “0” is converted to “1” and “1” is converted to “0” of the one code word (referred to as total inversion operation hereinafter), and thus the one code word is converted to the other code word.
There are 88992 code words that have the start point state of the state (7, 7) and satisfy the third restriction (in this case (2)) out of code words that satisfy the second restriction (124416 code words), and there are 88992 code words that have the start point state of the state (3, 3) and satisfy the third restriction (in this case (1)), these code words are in the total inversion code relation each other.
Therefore, for example, the code words coded with the start point state fixed at the state (7, 3) are converted easily to the code words having the start point state of the state (3, 7) by applying total inversion operation. Similarly, the code words coded with the start point state fixed at the state (7, 7) are converted easily to the code words having the start point state of the state (3, 3).
However, in the finite state transition diagram shown in FIG. 3, the code words that have the start point state of the state (7, 3) and satisfy the third restriction and the code words that have the start point state of the state (7, 7) and satisfy the third restriction are not in total inversion relation each other. Similarly, the code words that have the start point state of the state (3, 3) and satisfy the third restriction and the code words that have the start point state of the state (3, 7) and satisfy the third restriction are not in total inversion relation each other.
Therefore, the code words coded with the start point state fixed at the state (7, 3) are converted not easily to the code words having the start point state of the state (7, 7), and the code words coded with the start point state fixed at the state (3, 3) are converted not easily to the code words having the start point state of the state (3, 7). In view of the above, in the case of this example, 70773 code words that are accommodable for all the start point states out of 124416 code words that satisfy the second restriction are used by performing partial inversion in units of 2 bits.
All the code words that likely have the maximum sequential length Tmax of 10T are removed from these code words (70773 code words) by applying the fourth restriction, and arbitrary 65536 (=216) code words are selected from among the residual code words, and these code words are assigned to the data word.
As described above, the coding processing is performed.
FIG. 4 shows an exemplary structure of the decoder 17. A state detection circuit 31 receives the 20 bit code word detected by means of the code detector 16. The state detection circuit 31 detects the start point state (RDS and ADS, total 2 bits) of the code word from the input code word, and supplies the detected start point state to a code correction circuit 32 as the temporary state of the start point of the code word to be decoded this time. The state detection circuit 31 detects the type of the code word from the input code word, and supplies the code word type parity that indicates the detected type to the code word correction circuit 32.
The code word correction circuit 32 receives not only the temporary state of the start point and the code word type parity from the state detection circuit 31 but also the code word from the code detector 16 directly. The code word correction circuit 32 corrects the code word supplied from the code detector 16 based on the temporary state of the start point supplied from the state detection circuit 31 and the code word type indicated by means of the code word type parity, and supplies the corrected code word to a decoding circuit 33. The decoding circuit 33 decodes the code word supplied from the code correction circuit 32 to generate the 16 bit data word, and supplies the data word to the external apparatus.
FIG. 5 shows an ADS trellis diagram used for detecting MSN code to which PR1 equalization is applied. In the ADS trellis diagram, the least-square Euclidean distance is 4, and the maximum number of selectable states is 14. In FIG. 5, each square mark indicates a state, and white or black color on the square mark indicates the polarity (negative or positive) of a recording code in each state.
In the case of this example, the start point state or the end point state of the code is selected correspondingly to the set partitioning method, and QCS has been removed entirely from the code word that satisfies the condition of the trellis diagram. In other words, TD that indicates the maximum bit length for summing the minimum Euclidean distance is finite, and is 33 bits in this case. In other words, the number of minimum bits of the path memory required for the code detector 16 is 33 bits.
As described above, the recording/reproducing apparatus 1 performs coding processing and decoding processing. In the coding processing, for example, the maximum sequential length Tmax is as relatively large as 9T, PLL is unstable, the SN ratio of the equalization signal is poor, and the cross talk from the adjacent track is serious as described above. These disadvantages are the problem in the coding processing.
Furthermore, in the decoding processing, for example, the maximum number of possible states in the ADS Nyquist diagram shown in FIG. 5 is as large as 14, and it is necessary to reduce the number for higher density recording. This disadvantage is the problem in decoding processing.
Furthermore, TD is 33 bits according to the ADS trellis diagram shown in FIG. 5, the path memory of 33 bits or more is needed, and the maximum number of selectable states is as large as 14. As the result, the apparatus (code detector 16) is inevitably large-sized, and the power consumption is large. These disadvantages are the problem.
Some characteristics in the case of 8/10 code of usual DC free code (code from which DC component is removed), which is practically used for DAT (digital audio tape recorder) that is one of digital audio system standards for consumer, DDS (digital data storage system) that is one of tape streamer standards, or AIT1 or the like, and in the case of 16/20 code (16/20 MSN code practically used in AIT2) used in this example are shown below:
MaximumNumber ofCodingnumber of“01”/“10”DetectorrateTmaxstatessequenceTDgain 8/104T21414+3 dB16/209T14933+6 dB
The detector gain represents the theoretical gain to the white noise in the code detector in the case that the gain is 0 dB during bit-by-bit detection.
The number of “01”/“10” sequence is the maximum number of sequential “01” or “10” in the NRZ code, if the number is large, then “0” continues sequentially in the equalization signal, PLL becomes unstable, and it takes a long time to establish a path disadvantageously when the partial response equalization system, in which Nyquist frequency component of the transmission function becomes null, such as PR1 equalization, PR2 equalization, or PR4 equalization is applied. In other words, in this case, not only the maximum number of states Tmax but also the number of “01”/“10” sequence is desirably short. However, in the case of MSN code in which ADS is finite and the Nyquist frequency component of the code spectrum is null, the number of “01”/“10” sequence is not the problem because the number of “01”/“10” sequence is equal to or smaller than (ADS-1).
Though the data error rate during decoding can be improved by correcting the code detection error during decoding, the apparatus for performing such error correction is not disclosed, and the error correction cannot be therefore performed disadvantageously.